FPGA：Verilog中#的用法

刘颜儿发布时间：2022-06-06 19:41:59 ，浏览量：3

用于testbench文件中的延迟

`timescale 1ns/1ps // 含义为：时延单位为1ns，时延精度为1ps
// 格式：#延迟的时间
#20//延迟20ns

用于parameter在实例化时修改参数值

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FPGA：Verilog中#的用法

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