图像处理2:均值滤波

前言 正文 重点

1. 生成一个3×3的矩阵
2. 注意信号的同步

//均值滤波
module mean_filter
(
		//global clock
		input					clk,  				//cmos video pixel clock
		input					rst_n,				//global reset
	
		//Image data prepred to be processd
		input					per_frame_vsync,	//Prepared Image data vsync valid signal
		input					per_frame_href,		//Prepared Image data href vaild  signal
		input					per_frame_clken,	//Prepared Image data output/capture enable clock
		input		[7:0]		per_img_Y,			//Prepared Image brightness input
		
		//Image data has been processd
		output					post_frame_vsync,	//Processed Image data vsync valid signal
		output					post_frame_href,	//Processed Image data href vaild  signal
		output					post_frame_clken,	//Processed Image data output/capture enable clock
		output		[7:0]		post_img_Y			//Processed Image Bit flag outout(1: Value, 0:inValid)
		
);

	//----------------------------------------------------
	//Generate 8Bit 3X3 Matrix for Video Image Processor.
	//Image data has been processd
	wire				matrix_frame_vsync;	//Prepared Image data vsync valid signal
	wire				matrix_frame_href;	//Prepared Image data href vaild  signal
	wire				matrix_frame_clken;	//Prepared Image data output/capture enable clock	
	wire		[7:0]	matrix_p11, matrix_p12, matrix_p13;	//3X3 Matrix output
	wire		[7:0]	matrix_p21, matrix_p22, matrix_p23;
	wire		[7:0]	matrix_p31, matrix_p32, matrix_p33;


	// 使用Shift_RAM_3X3  构建3X3的模板
	Shift_RAM_3X3 Shift_RAM_3X3_inst
	(
		//global clock
		.clk							(clk),  				//cmos video pixel clock
		.rst_n							(rst_n),				//global reset
		.per_frame_vsync				(per_frame_vsync),		//Prepared Image data vsync valid signal
		.per_frame_href					(per_frame_href),		//Prepared Image data href vaild  signal
		.per_frame_clken				(per_frame_clken),		//Prepared Image data output/capture enable clock
		.per_img_Y						(per_img_Y),			//Prepared Image brightness input
	
		//Image data has been processd
		.matrix_frame_vsync				(matrix_frame_vsync),	//Prepared Image data vsync valid signal
		.matrix_frame_href				(matrix_frame_href),	//Prepared Image data href vaild  signal
		.matrix_frame_clken				(matrix_frame_clken),	//Prepared Image data output/capture enable clock	
		
		.matrix_p11(matrix_p11),	.matrix_p12(matrix_p12), 	.matrix_p13(matrix_p13),	//3X3 Matrix output
		.matrix_p21(matrix_p21), 	.matrix_p22(matrix_p22), 	.matrix_p23(matrix_p23),
		.matrix_p31(matrix_p31), 	.matrix_p32(matrix_p32), 	.matrix_p33(matrix_p33)
);

	
	//---------------------------------------------//
	//step1：每行数据相加
	reg [9:0] mean_value1;
	reg [9:0] mean_value2;
	reg [9:0] mean_value3;
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n) 
			begin
				mean_value1