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Vivado HLS创建AXI LITE接口

FPGA硅农 发布时间:2020-03-02 23:03:25 ,浏览量:2

HLS AXI LITE接口

AXI LITE接口每次只能传输一个数据,因此经常用来传输PS和PL之间的命令、状态等信息。

HLS代码如下
#include
typedef ap_int dt;
dt axilite(dt a,dt b,dt *c){
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_CTRL
#pragma HLS INTERFACE s_axilite port=a bundle=BUS_IN
#pragma HLS INTERFACE s_axilite port=b bundle=BUS_IN
#pragma HLS INTERFACE s_axilite port=c bundle=BUS_INOUT
   *c=a+b;
   return a*b;
}

生成的PS端的API函数见ip文件夹内的driver,具体路径记不清了。

Block Design

连接AXI GPIO MASTER和AXI LITE SLAVE即可(RUN AUTO CONNECTION)

CPU端代码
#include "xAxilite.h" // Device driver for HLS HW block
#include "xparameters.h"
// HLS HW instance
XAxilite HlsAxilite;
XAxilite_Config *AxilitePtr;
int main() {
int res_hw;
// Look Up the device configuration
AxilitePtr = XAxilite_LookupConfig(XPAR_XAXILITE_0_DEVICE_ID);
if (!AxilitePtr) {
print("ERROR: Lookup of accelerator configuration failed.\n\r");
return XST_FAILURE;
}
// Initialize the Device
int status = XAxilite_CfgInitialize(&HlsAxilite, AxilitePtr);
if (status != XST_SUCCESS) {
print("ERROR: Could not initialize accelerator.\n\r");
exit(-1);
}
//Set the input parameters of the HLS block
XAxilite_Set_a_V(&HlsAxilite, 24);
XAxilite_Set_b_V(&HlsAxilite, 12);
// Start the device and read the results
XAxilite_Start(&HlsAxilite);
do {
res_hw = XAxilite_Get_c_V(&HlsAxilite);
} while (XAxilite_Get_c_V_vld(&HlsAxilite) == 0); // wait for valid data output
print("Detected HLS peripheral complete. Result received.\n\r");
printf("*c=%d\n",res_hw);
printf("return=%d\n",XAxilite_Get_return(&HlsAxilite));
}

c应该为a+b=36,return应为ab=288,输出结果不出所料: 在这里插入图片描述

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