MIPS五级流水线（含data hazard)

设计参考图

旁路单元

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:30:49
// Design Name: 
// Module Name: FORWARDING
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module FORWARDING(
input [4:0]ID2EXE_rs,
input [4:0]ID2EXE_rt,
input [4:0]EXE2MEM_RegRd,
input [4:0]MEM2WB_RegRd,
input EXE2MEM_RegWrite,
input MEM2WB_RegWrite,
output reg [1:0]ForwardA,
output reg [1:0]ForwardB
);
//ForwardA
always@(*)
begin
if(EXE2MEM_RegWrite==1&&(EXE2MEM_RegRd!=0)&&EXE2MEM_RegRd==ID2EXE_rs)
    ForwardA=2'b10;                                       // 来自EXE/MEM
else if(MEM2WB_RegWrite==1&&(MEM2WB_RegRd!=0)&&MEM2WB_RegRd==ID2EXE_rs)
    ForwardA=2'b01;                                       // 来自MEM/WB
else
    ForwardA=2'b00;                                       // 来自ID/EXE
end                                                      
//ForwardB
always@(*)
begin
if(EXE2MEM_RegWrite==1&&(EXE2MEM_RegRd!=0)&&EXE2MEM_RegRd==ID2EXE_rt)
    ForwardB=2'b10;
else if(MEM2WB_RegWrite==1&&(MEM2WB_RegRd!=0)&&MEM2WB_RegRd==ID2EXE_rt)
    ForwardB=2'b01;
else
    ForwardB=2'b00;
end

endmodule

冒险检测单元

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:44:46
// Design Name: 
// Module Name: HAZARD_DETECTION
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module HAZARD_DETECTION(
input ID2EXE_MemRead,
input [4:0]ID2EXE_rt,
input [4:0]IF2ID_rs,
input [4:0]IF2ID_rt,
output reg PCWrite,
output reg IF2ID_Write,
output reg ID2EXE_Stall
    );
always@(*)
begin
if(ID2EXE_MemRead&&((ID2EXE_rt==IF2ID_rs)||(ID2EXE_rt==IF2ID_rt)))               //流水线阻塞1个clk
begin
    ID2EXE_Stall=1'b1;                                  //ID2EXE段的控制命令清0                           
    PCWrite=1'b0;                                       //PC保持不变
    IF2ID_Write=1'b0;                                   //IF2ID段寄存器保持不变
end
else
begin
    ID2EXE_Stall=1'b0;
    PCWrite=1'b1;
    IF2ID_Write=1'b1;
end
end

endmodule

ALUSrc多路选择器

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:55:12
// Design Name: 
// Module Name: mux3_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module mux3_1(
input [31:0]a,
input [31:0]b,
input [31:0]c,
input [1:0]select,
output reg [31:0]out
    );
always@(*)
case (select)
    2'b00:out=a;
    2'b10:out=b;
    2'b01:out=c; 
    default:out=32'd0;
endcase
endmodule

总体代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/23 15:31:35
// Design Name: 
// Module Name: MIPS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module MIPS(
input clk,
input rst
    );
reg [31:0] RegFile [0:31];
reg [31:0] IMEM [0:255];
reg [31:0] DMEM [0:255];

integer i;
initial
begin
    for(i=0;i