MIPS(pipeline+harzard)

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/23 15:31:35
// Design Name: 
// Module Name: MIPS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module MIPS(
input clk,
input rst
    );
reg [31:0] RegFile [0:31];
reg [31:0] IMEM [0:255];
reg [31:0] DMEM [0:255];

integer i;
initial
begin
    for(i=0;i