system verilog实现矩阵乘法

本代码实现了NxN矩阵和NxN矩阵的乘法，当然矩阵不一定非要是方阵，只需对代码稍作修改即可。 在本代码中，矩阵乘法是分块进行的，且在加载块矩阵和计算块矩阵部分和间加入乒乓操作，同时，也在计算块矩阵和写回块矩阵之间加入了乒乓操作，因此，数据传输（包括加载和写回)时间被掩盖，吞吐率得到提升。 下面是顶层模块的代码：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/17 21:51:58
// Design Name: 
// Module Name: compute_mm
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module compute_mm(               //O=A*B
input logic clk,
input logic rst,
input logic start,
input logic [15:0]dina,          //读取矩阵A
input logic [15:0]dinb,          //读取矩阵B
output logic [7:0]addra,        
output logic [7:0]addrb,
output logic we,                 //结果写入O矩阵
output logic [7:0]addro,
output logic [15:0]douto,
output logic done
    );
parameter N = 16;
parameter Tn = 4;

logic [15:0]buff_o1[0:Tn-1][0:Tn-1];
logic [15:0]buff_o2[0:Tn-1][0:Tn-1];
logic [7:0]block_row;
logic [7:0]block_col;
logic [7:0]pre_block_row;                 //compute block and store pre_block
logic [7:0]pre_block_col;

logic pingpang;
logic pingpang_start;
logic pingpang_done;

logic start_compute1;
logic start_compute2;
logic start_store1;
logic start_store2;
logic compute1_done;
logic compute2_done;
logic store1_done;
logic store2_done;
logic compute1_done_ff;
logic compute2_done_ff;
logic store1_done_ff;
logic store2_done_ff;

logic we1;
logic we2;
logic [7:0]addro1;
logic [7:0]addro2;
logic [15:0]douto1;
logic [15:0]douto2;
logic [7:0]addra1;
logic [7:0]addra2;
logic [7:0]addrb1;
logic [7:0]addrb2;

logic first_compute;
logic final_store;
logic busy;
//busy
always_ff@(posedge clk,posedge rst)
if(rst)
   busy