基于FPGA的VGA控制器

时序图 因此,hsync和vsync信号延迟4个clk.

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/12/09 09:06:45
// Design Name: 
// Module Name: vga_controller
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module vga_controller(
input clk,
input rst,
input [3:0]num,
output  hs,
output  vs,
output reg R,
output reg G,
output reg B
    );
parameter HS_CNT=96;
parameter H_FP_CNT=16;
parameter H_BP_CNT=48;
parameter HDISP_CNT=640;       //和为800

parameter VS_CNT=2;
parameter V_FP_CNT=10;
parameter V_BP_CNT=29;
parameter VDISP_CNT=480;        //和为521
//variables
reg [11:0]h_cnt;
reg [11:0]v_cnt;


reg disp,disp_ff1,disp_ff2,disp_ff3;
reg hsync,hsync_ff1,hsync_ff2,hsync_ff3,hsync_ff4;
reg vsync,vsync_ff1,vsync_ff2,vsync_ff3,vsync_ff4;
reg [13:0]addr;

wire [2:0]dout;
wire [9:0]pix_row;
wire [9:0]pix_col;
reg [9:0]pix_row_ff1;
reg [9:0]pix_row_ff2;
reg [9:0]pix_row_ff3;
reg [9:0]pix_row_ff4;
reg [9:0]pix_col_ff1;
reg [9:0]pix_col_ff2;
reg [9:0]pix_col_ff3;
reg [9:0]pix_col_ff4;
//pix_col and pix_row delay 3 clk
always@(posedge clk,posedge rst)
if(rst)
begin
    {pix_row_ff1,pix_row_ff2,pix_row_ff3,pix_row_ff4}