Zynq开发-通过寄存器读写调用HLS IP核

一般情况下，在使用Vivado HLS工具将设计导出为RTL IP时，会附带一个在Xilinx SDK中调用HLS IP核的驱动程序，我们可以直接使用已经写好的驱动程序来使用PL端的ip来为我们做一些计算，本文则旨在直接通过读写寄存器来进行HLS IP的调用。 HLS IP的设计流程以及Vivado中的Block Deisgn在这里略去，主要讲如何使用寄存器来控制我们的IP。 首先我们在system.hdf中查看HLS IP核的寄存器地址： 因为不使用中断，我们主要关心以下三个寄存器地址 在HLS提供的驱动文件中，我们能看到更详细的信息 可以看到，控制信号中，低4位分别是ap_ready、ap_idle、ap_done和ap_start信号，第8位（也就是bit7)是自动重启的信号。因此，我们可以编写如下代码调用HLS IP：

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/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include 
#include "platform.h"
#include "xil_printf.h"
#include "xparameters.h"
#include "xmy_cnn.h"
#include"xil_cache.h"
#include "xil_io.h"

u32 myip_isdone(int addr){
	u32 Data;
	Data=Xil_In32(addr);
	return (Data >> 1) & 0x1;
}


int main()
{
    //u32 a=0x10000000;
    //u32 b=0x10001000;
	int* a=(int*)malloc(sizeof(int)*20);
	int* b=(int*)malloc(sizeof(int)*20);
	//int a[30];
	//int b[30];
    int i;
	init_platform();
    for(i=0;i> 1) & 0x1)
    		break;
    }
    Xil_DCacheInvalidateRange((u32)b,20*sizeof(int));
    for(i=0;i> 1) & 0x1;
}


int main()
{
    //u32 a=0x10000000;
    //u32 b=0x10001000;
	//int* a=(int*)malloc(sizeof(int)*20);
	//int* b=(int*)malloc(sizeof(int)*20);
	int a[20];
	int b[20];
    int i;
	init_platform();
    for(i=0;i> 1) & 0x1)
    		break;
    }
    Xil_DCacheInvalidateRange((u32)b,20*sizeof(int));
    for(i=0;i> 1) & 0x1;
}


int main()
{
    //u32 a=0x10000000;
    //u32 b=0x10001000;
	int* a=(int*)malloc(sizeof(int)*20);
	int* b=(int*)malloc(sizeof(int)*20);
	//int a[20];
	//int b[20];
    int i;
	init_platform();
    for(i=0;i> 2) & 0x1)
    		break;
    }
    Xil_Out32(0x43c00010,(u32)a);
    Xil_Out32(0x43c00018,(u32)b);
    Xil_Out32(0x43c00000,(u32)0x01);
    while(1){
    	u32 Data;
    	Data=Xil_In32(0x43c00000);
    	if((Data >> 1) & 0x1)
    		break;
    }
    Xil_DCacheInvalidateRange((u32)b,20*sizeof(int));
    for(i=0;i> 1) & 0x1;
}


int main()
{
    //u32 a=0x10000000;
    //u32 b=0x10001000;
	//int* a=(int*)malloc(sizeof(int)*20);
	//int* b=(int*)malloc(sizeof(int)*20);
	int a[20];
	int b[20];
    int i;
	init_platform();
    for(i=0;i> 2) & 0x1)
    		break;
    }
    Xil_Out32(0x43c00010,(u32)a);
    Xil_Out32(0x43c00018,(u32)b);
    Xil_Out32(0x43c00000,(u32)0x01);
    while(1){
    	//volatile u32 Data
    	u32 Data2;
    	Data2=Xil_In32(0x43c00000);
    	if((Data2 >> 1) & 0x1)
    		break;
    }
    Xil_DCacheInvalidateRange((u32)b,20*sizeof(int));
    Xil_DCacheInvalidateRange((u32)a,20*sizeof(int));
    for(i=0;i