基于FPGA的TPU脉动阵列

部分信号的时序图：

模块代码：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/02/05 19:33:34
// Design Name: 
// Module Name: systolic
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module systolic(       //计算A*B,其中A为nxn,B为nxk，A存储在pe_array中固定
input logic clk,
input logic rst,

input logic [15:0]k, 
input logic start_compute,
input logic start_load,
output logic compute_done,
output logic load_done,

input logic [15:0] data_a [0:N-1],            //A,存在weight中
input logic [15:0] data_b [0:N-1],            //输入数据
output logic [15:0] addra [0:N-1],
output logic [15:0] addrb [0:N-1],

output logic [15:0] addro [0:N-1],
output logic [31:0] data_o [0:N-1],
output logic weo [0:N-1]
);

parameter N = 4;

logic busy;
logic busy_ff1;
logic busy_for_shift;
logic busy_for_calc;
logic busy_for_store;

logic [9:0] count;                  //for compute
logic [9:0] count_ff1;
logic [9:0] count_for_shift;
logic [9:0] count_for_calc;
logic [9:0] count_for_store;

logic [9:0] count_for_load;
logic [9:0] count_for_load_ff1;
logic [9:0] count_for_load_ff2;
logic busy_for_load;
logic busy_for_load_ff1;
logic busy_for_load_ff2;

logic [15:0] data [0:N-1][0:N-1];
logic [15:0] weight [0:N-1][0:N-1];
logic [31:0] psum [0:N-1][0:N-1];

//load task
//busy_for_load
always_ff@(posedge clk,posedge rst)
if(rst)
    busy_for_load