AXI STREAM协议学习

axi stream协议的具体内容可参见从零学习AXI4总线(二)：AXI4-Stream 介绍和AXI4-Stream协议总结 以下是一个简单的HDL示例，完成的功能是master向slave写入512个数据(1,2,3,…,511,512) 主机代码:

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/06/13 20:42:20
// Design Name: 
// Module Name: axis_master
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module axis_master(
input logic ACLK,
input logic ARESETn,
input logic start,
input logic TREADY,
output logic done,
output logic TVALID,
output logic [31:0] TDATA,
output logic [3:0] TSTRB,
output logic [3:0] TKEEP,
output logic TLAST,
output logic TID,                       
output logic TDEST,                    
output logic TUSER                      //TID,TDEST,TUSER用于多机通信
    );
    
parameter N=512;
logic [31:0] tx_buffer [0:N-1];        //待传输的值
logic [31:0] tx_cnt;
//初始化tx_buffer
always_ff@(posedge ACLK,negedge ARESETn) 
if(~ARESETn)
begin
    for(int i=0;i