CRC循环冗余校验码的Verilog实现

原理见博客

设计文件：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/23 14:32:17
// Design Name: 
// Module Name: crc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module crc(
input logic clk,
input logic rst,
input logic req,                              //请求信号，拉高一个周期
input logic [5:0]i_data,                      //6位
input logic [3:0]i_crc,                       //4位
output logic [8:0]o_data,                   //6+4-1=9位
output logic o_vld
    );

logic [3:0] crc_r;
logic [8:0] data_r;
logic [3:0] tmp;
logic [9:0] count;
logic busy;
//crc_r,data_r
always_ff@(posedge clk,posedge rst)
if(rst)
begin
    crc_r