RISC-V CPU设计(二)---数据通路

FPGA硅农发布时间：2022-03-11 14:48:08 ，浏览量：0

本文讲述五级流水线RISC-V CPU数据通路，我们采用的是如下图所示的架构在这里插入图片描述

R型指令的数据通路 IF阶段

根据PCF读取指令，并将PCF和读取到的指令寄存到IF2ID段寄存器： PCD

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RISC-V CPU设计(二)---数据通路

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