1.add.v
module add (a,b,c,g,p,s);
input a,b,c;
output g,p,s;
assign s = a ^ b ^ c;
assign g = a & b;
assign p = a | b;
endmodule
2.addsub32.v
module addsub32 (a, b, sub, s);
input [31:0] a, b;
input sub;
output [31:0] s;
cla32 as32 (a, b^{32{sub}}, sub, s);
endmodule
3.alu.v
module alu(a,b,aluc,r,z);
input [31:0] a,b;
input [3:0] aluc;
output [31:0] r;
output z;
wire [31:0] d_and = a & b;
wire [31:0] d_or = a | b;
wire [31:0] d_xor = a ^ b;
wire [31:0] d_lui = {b[15:0],16'h0};
wire [31:0] d_and_or = aluc[2]? d_or : d_and;
wire [31:0] d_xor_lui = aluc[2]? d_lui : d_xor;
wire [31:0] d_as /*synthesis keep*/;
wire [31:0] d_sh /*synthesis keep*/;
addsub32 as32 (a,b,aluc[2],d_as);
shift shifter (b,a[4:0],aluc[2],aluc[3],d_sh);
mux4x32 select (d_as,d_and_or,d_xor_lui,d_sh,aluc[1:0],r);
assign z = ~|r;
endmodule
4.cla_2.v
module cla_2 (a,b,c_in,g_out,p_out,s);
input [1:0] a,b;
input c_in;
output g_out,p_out;
output [1:0] s;
wire [1:0] g,p;
wire c_out;
add add0 (a[0],b[0],c_in,g[0],p[0],s[0]);
add add1 (a[1],b[1],c_out,g[1],p[1],s[1]);
g_p g_p0 (g,p,c_in,g_out,p_out,c_out);
endmodule
5.cla_4.v
module cla_4 (a,b,c_in,g_out,p_out,s);
input [3:0] a,b;
input c_in;
output g_out,p_out;
output [3:0] s;
wire [1:0] g,p;
wire c_out;
cla_2 cla0 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]);
cla_2 cla1 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]);
g_p g_p0 (g,p,c_in,g_out,p_out,c_out);
endmodule
6.cla_8.v
module cla_8 (a,b,c_in,g_out,p_out,s);
input [7:0] a,b;
input c_in;
output g_out,p_out;
output [7:0] s;
wire [1:0] g,p;
wire c_out;
cla_4 cla0 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]);
cla_4 cla1 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]);
g_p g_p0 (g,p,c_in,g_out,p_out,c_out);
endmodule
7.cla_16.v
module cla_16 (a,b,c_in,g_out,p_out,s);
input [15:0] a,b;
input c_in;
output g_out,p_out;
output [15:0] s;
wire [1:0] g,p;
wire c_out;
cla_8 cla0 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]);
cla_8 cla1 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]);
g_p g_p0 (g,p,c_in,g_out,p_out,c_out);
endmodule
8.cla_32.v
module cla_32 (a,b,c_in,g_out,p_out,s);
input [32:0] a,b;
input c_in;
output g_out,p_out;
output [31:0] s;
wire [1:0] g,p;
wire c_out;
cla_16 cla0 (a[15:0],b[15:0], c_in, g[0],p[0],s[15:0]);
cla_16 cla1 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]);
g_p g_p0 (g,p,c_in,g_out,p_out,c_out);
endmodule
9.cla32.v
module cla32 (a,b,ci,s,co);
input [31:0] a,b;
input ci;
output [31:0] s;
output co;
wire g_out,p_out;
cla_32 cla (a,b,ci,g_out,p_out,s);
assign co = g_out | p_out & ci;
endmodule
10.g_p.v
module g_p (g,p,c_in,g_out,p_out,c_out);
input [1:0] g,p;
input c_in;
output g_out,p_out,c_out;
assign g_out = g[1] | p[1] & g[0];
assign p_out = p[1] & p[0];
assign c_out = g[0] | p[0] & c_in;
endmodule
11.mux2x5.v
module mux2x5 (a0,a1,s,y);
input [4:0] a0,a1;
input s;
output [4:0] y;
assign y = s? a1:a0;
endmodule
12.mux2x32.v
module mux2x32 (a0,a1,s,y);
input [31:0] a0,a1;
input s;
output [31:0] y;
assign y = s? a1 : a0;
endmodule
13.mux4x32.v
module mux4x32 (a0,a1,a2,a3,s,y);
input [31:0] a0,a1,a2,a3;
input [1:0] s;
output [31:0] y;
function [31:0] select;
input [31:0] a0,a1,a2,a3;
input [1:0] s;
case (s)
2'b00: select = a0;
2'b01: select = a1;
2'b10: select = a2;
2'b11: select = a3;
endcase
endfunction
assign y = select(a0,a1,a2,a3,s);
endmodule
14.shift.v
module shift (d,sa,right,arith,sh);
input [31:0] d;
input [4:0] sa;
input right,arith;
output [31:0] sh;
reg [31:0] sh;
always @* begin
if (!right) begin
sh = d sa;
end else begin
sh = $signed(d) >>> sa;
end
end
endmodule
