chisel边沿检测电路实现（Reg延迟特性）

一、代码设计

• chisel代码

import chisel3._
import chisel3.util._
import chisel3.stage._

class EdgeDetect(resetValue: Option[UInt] = None) extends Module {
    val io = IO(new Bundle {
        val in  = Input(UInt(1.W))
        val pos = Output(UInt(1.W))
        val neg = Output(UInt(1.W))
    })
    val reg = if (resetValue.isDefined) { // resetValue = Some(number)
        RegInit(resetValue.get)
    } else { //resetValue = None
        Reg(UInt())
    }
    
    reg := io.in
    
    when((reg===0.U)&&(io.in===1.U)){
        io.pos := 1.U
        io.neg := 0.U
    }.elsewhen((reg===1.U)&&(io.in===0.U)){
        io.pos := 0.U
        io.neg := 1.U
    }.otherwise {
        io.pos := 0.U
        io.neg := 0.U
    }
        
}

// Generate the Verilog code
object EdgeDetectMain extends App {
  println("Generating the EdgeDetect hardware")
  
  (new chisel3.stage.ChiselStage).execute(Array("--target-dir", "generated"), 
  							Seq(ChiselGeneratorAnnotation(() => new EdgeDetect(Some(1.U)))))
}

• 生成的verilog代码主体部分

module EdgeDetect(
  input   clock,
  input   reset,
  input   io_in,
  output  io_pos,
  output  io_neg
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  reg_; // @[EdgeDetect.scala 14:16]
  wire  _T_5 = reg_ & ~io_in; // @[EdgeDetect.scala 24:27]
  assign io_pos = ~reg_ & io_in; // @[EdgeDetect.scala 21:21]
  assign io_neg = ~reg_ & io_in ? 1'h0 : _T_5; // @[EdgeDetect.scala 21:37 EdgeDetect.scala 23:16]
  always @(posedge clock) begin
    reg_